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MOUNTAIN VIEW, Calif.----Oct. 26, 2000-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, today announced the global release of the LEDA® 2.5 family of hardware description language (HDL) checkers. The new version delivers advanced chip-level checking capabilities and pre-packaged rules, together with improved programmability and error-reporting features. The LEDA checkers enable companies to enforce coding-style guidelines across large design teams, and inspect the quality and workmanship of intellectual property (IP) blocks procured from different vendors.

``American Microsystems, Inc. (AMI) is very pleased with the advanced new features in the LEDA checkers,'' said Erik Comparini, design methodology manager for American Microsystems, Inc. ``We have now been using the LEDA checkers for several months to develop coding-style rules to enable RTL hand-off between AMI and its customers. We expect the new chip-level capabilities in the LEDA checkers will let us check for many critical design rules that we were unable to handle before, and thus audit the quality of customer designs as well as internally and externally developed IP blocks more effectively.''

``Over the last year, the interest-level for HDL checkers has grown tremendously,'' said John Chilton, senior vice-president and general manager of the IP and Systems Group at Synopsys. ``With designs today typically containing hundreds of thousands of lines of RTL code and being done with geographically dispersed teams, designers need automated methods for checking that good design practices are being followed and company standards are being met. Otherwise there is a potential for needless design-iterations and bottlenecks that ultimately result in lost market opportunities.''

Setting a New Standard for Easy-Programmability

Most programmable HDL checkers available today require the designer to program rules using C/C++, PERL, or Tool Command Language (TCL) together with a complex application-programming interface (API). The LEDA checkers rely instead on a simple command set to manipulate HDL ``language-attributes'' taken from the language reference manual. The key advantage is that any rule that can be formalized in terms of Verilog or VHDL constructs, can be easily programmed and checked by the LEDA checkers. To facilitate programming rules even further, LEDA 2.5 includes a ``rule-creation wizard'' that lets designers customize more than 50 commonly used coding-style rules by selecting different configuration parameters using a GUI.

    Linkage to Other Synopsys Tools Will Deliver Increased Design Flow
    Productivity

Because EDA tools differ in the particular HDL subsets they support, designers often run into bottlenecks when they fail to constrain their HDL code to a syntactic/semantic subset compatible with all the tools in the design flow. To solve this problem, Synopsys has announced plans to deliver pre-packaged rulesets with the LEDA checkers that check code for optimum performance with other Synopsys tools, starting in early 2001. The first available rulesets will be for Design Compiler(TM) and VCS(TM) Synopsys plans to follow up with additional rulesets for other tools such as Primetime®, Scirocco(TM) and Formality® later in that year. These rulesets will be regularly updated and maintained to reflect new features and capabilities as they are added to new Synopsys releases.

Pricing and Availability

The LEDA Rule Checker and Specifier are priced respectively starting at $10,000 and $15,000 US for a one-year Technology Subscription License (TSL). The 2.5 version of the LEDA Checkers is available now.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys, LEDA, Formality and Primetime are registered trademarks of Synopsys, Inc. Design Compiler, VCS and Scirocco are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys, Inc., Mountain View
     Meghan Le, 650/584-4832
     meghan@synopsys.com
        or
     KVO Public Relations
     Judy Kahn, 650/919-2022
     judy_kahn@kvo.com